Akademisyen

ENGİN AFACAN

DOÇENT

GEBZE TEKNİK ÜNİVERSİTESİ MÜHENDİSLİK FAKÜLTESİ ELEKTRONİK MÜHENDİSLİĞİ BÖLÜMÜ

Ana Dal Mühendislik Temel Alanı
Yan Dal Elektrik-Elektronik Mühendisliği

Kayıtlı çıktılara kısa bakış — ayrıntılar aşağıda.

Makale 24
Proje 0
Kitap 0
Bildiri 55
Patent 0
Sanatsal 0

Scopus (SJR) Q1 3 Q2 6 Q3 10 Q4 2

WoS (JCR) Q1 1 Q2 5 Q3 8 Q4 8

TR Index 0 makale

Alan+yıl+tür normalize OpenAlex yüzdelik — Clarivate ESI / SciVal değildir.

Üst %1 makale 1

Üst %10 makale 2

Ort. yüzdelik 58.3%

Üst %1 payı 5.9%

Üst %10 payı 11.8%

Makaleler

YÖKSİS ve OpenAlex kaynak ayrımıyla makaleler; quartile ve TR Index ile daraltabilirsiniz.

Makale listesi

2026 MORL-IC: Multi-objective reinforcement learning approaches for analog integrated circuit optimization Integration DOI 10.1016/j.vlsi.2026.102664 YÖKSİS SJR Q2 JCR Q3 OpenAlex 83.6%
2026 A Fully Automated SPICE-Compatible Netlist Extraction From Image Using Deep Learning and Image Preprocessing Techniques IEEE Access DOI 10.1109/ACCESS.2026.3656316 YÖKSİS SJR Q1 JCR Q2 OpenAlex 6.0%
2025 A Fully Automated Robotic System for Tuning Optimization of RF Cavity Filter Journal of Field Robotics DOI 10.1002/rob.22547 YÖKSİS SJR Q1 JCR Q2 OpenAlex 55.0%
2023 MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark Association for Computing Machinery (ACM) DOI 10.1145/3626096 YÖKSİS SJR Q2 JCR Q2 OpenAlex 86.9%
2020 Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi DOI 10.16984/saufenbilder.726396 YÖKSİS SJR Q4 OpenAlex 7.5%
2019 On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS DOI 10.1145/3325069 YÖKSİS SJR Q2 JCR Q4 OpenAlex 43.6%
2017 Aging signature properties and an efficient signature determination tool for online monitoring Integration, the VLSI Journal DOI 10.1016/j.vlsi.2017.03.002 YÖKSİS SJR Q3 JCR Q4 OpenAlex 1.5%
2017 A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology Journal of Electrical Engineering-Elektrotechnicky Casopis DOI 10.1515/jee-2017-0076 YÖKSİS SJR Q3 JCR Q4 OpenAlex 47.0%
2016 A lifetime aware analog circuit sizing tool Integration, the VLSI Journal DOI 10.1016/j.vlsi.2016.05.004 YÖKSİS SJR Q3 JCR Q4 OpenAlex 76.0%
2016 An analog circuit synthesis tool based on efficient and reliable yield estimation Microelectronics Journal DOI 10.1016/j.mejo.2016.05.002 YÖKSİS JCR Q3 OpenAlex 68.0%
2014 Reliability assessment of CMOS differential cross coupled LC oscillators and a novel on chip self healing approach against aging phenomena Microelectronics Reliability DOI 10.1016/j.microrel.2013.08.013 YÖKSİS SJR Q2 JCR Q2 OpenAlex 69.1%
2025 Reinforcement learning in integrated circuits: Design, synthesis, layout, and hardware security Integration DOI 10.1016/j.vlsi.2025.102460 YÖKSİS SJR Q2 JCR Q3 OpenAlex üst %10 OpenAlex 92.6%
2023 Radiation-aware analog circuit design via fully-automated simulation environment Elsevier BV DOI 10.1016/j.vlsi.2023.01.009 YÖKSİS SJR Q3 JCR Q3 OpenAlex 59.7%
2023 Autonomous RF Cavity Filter Tuning INSTRUMENTATION AND MEASUREMENT DOI https://ieeexplore.ieee.org/xpl/aboutJournal.jsp?punumber=5289 YÖKSİS SJR Q1 JCR Q1
2022 Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool Elsevier BV DOI 10.1016/j.vlsi.2022.02.009 YÖKSİS SJR Q3 JCR Q3 OpenAlex 83.5%
2021 Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis Integration DOI 10.1016/j.vlsi.2021.08.006 YÖKSİS SJR Q3 JCR Q4 OpenAlex 53.5%
2021 Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test Integration DOI 10.1016/j.vlsi.2020.11.006 YÖKSİS SJR Q3 JCR Q4 OpenAlex üst %1 OpenAlex 99.0%
2020 An efficient reliability simulation tool for lifetime-aware analog circuit synthesis Turkish Journal of Electrical Engineering and Computer Sciences YÖKSİS SJR Q3 JCR Q3
2020 Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm technology Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi DOI https://dergipark.org.tr/tr/doi/10.16984/saufenbilder.726396 YÖKSİS SJR Q4
2019 Inversion coefficient optimization based Analog/RF circuit design automation MICROELECTRONICS JOURNAL YÖKSİS JCR Q3

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